1. Field of the Invention
This invention relates in general to semiconductor devices and in particular to a metal insulator field effect transistor having a graded silicon germanium channel for improved transconductance.
2. Description of the Prior Art
Field effect transistors are horizontal devices including a source, a drain spaced from the source and a gate disposed between the source and the drain. A channel region lies underneath the gate and between the source and the drain. A metal insulator field effect transistor (MISFET) has a metal electrode affixed to an insulator layer disposed on top of the channel. A voltage imposed upon the gate electrode controls the flow of current from the source to the drain within the channel.
One of the disadvantages of silicon as a semiconductor is its hole mobility compared to its electron mobility. The passage of electrons through silicon is limited by the crystal lattice structure. Other materials, such as germanium, have different energy band structures resulting in higher carrier mobilities. Such higher carrier mobilities are desirable because the mobility of carriers ultimately determines the switching speed of the device. The faster the switching speed, the more operations the given device can perform within a given unit of time.
Silicon-germanium alloys can be grown commensurate on a silicon substrate so long as the alloy layer is thin enough. See, T. P. Pearsall, and J. C. Bean, "Enhancement- and depletion-mode p-channel Ge.sub.x Si.sub.1-x modulation doped FETs", IEEE Electron Device Letters, EDL-7, pp. 308-310, 1986, and R. C. Taft, J. D. Plummer and S. S. Iyer, "Fabrication of a p-channel BICFET in the Ge.sub.x Si.sub.1-x /Si system", International Electron Device Conf. Digest, pp. 570-573, 1988. Since the lattice spacing of a crystal of germanium is larger than the lattice of a crystal of silicon, a layer that includes an alloy of germanium and silicon is placed under strain when grown comensurately. The germanium crystal lattice is compressed and provides a so-called pseudomorphic layer. See K. Casper, "Growth Improprieties of Si/SiGe Superlattices" MSS-II Proceedings, page 703, Kyoto, Japan, September 1975; D. V. Lang et al., "Measurement of the Band Gap of Ge.sub.x Si.sub.1-x /Si Strained Layer Heterostructures", Applied Physics Letters, 47, page 1333 (1985). With such strained layers, several groups have demonstrated that two-dimensional electron and hole gas layers can be formed. It has recently been shown that the mobility of holes is higher in layers formed of an alloy of silicon and germanium than in pure silicon. See, P. J. Wang, et al., "Two-dimensional hole gas in Si/Si.sub.0.85 Ge.sub.0.15 /Si modulation-doped double heterostructures", Appl. Phys. Lett. Vol. 54, No. 26, p. 2701 (1989).
It is possible that the hole mobility in such a system is enhanced by the strain in the alloy layer which decreases the energy of the light hole band relative to the heavy hole band. In that system, the conduction and valence band discontinuities are relatively low compared to III-V compound materials. In addition, small Schottky barriers heights on silicon would make commercial utilization of the MODFET devices of Pearsall et al. very difficult because of high gate leakage current, particularly at room temperature.
European Patent 0 323 896 AZ discloses a conventional MOSFET device which incorporates a germanium channel region formed of 90-100% Ge in Si alloy. The channel is symmetric, where at each edge of the channel there is an identical transition region from the 90-100% Germanium in Silicon alloy to the surrounding regions of pure Si. Graded regions are provided at each channel edge to accomodate the well known lattice mismatch between silicon and germanium, that mismatch being 4.0%. This results in the generation of in excess of several thousand billion defects per square centimeter in this mostly germanium layer due to the severe mismatch between this layer's lattice constant and that of the Si substrate. Such defects are well known to limit carrier mobility. Apart from this mechanical consideration, the Ge profile in the channel, as in all other known prior art, is symmetric and uniform throughout the mostly Ge region. Thus, two active transport regions will be formed at the edges of this channel, one at the transition from the silicon substrate to the 90-100% germanium channel, and the other at the transition region back to pure silicon at the surface of the device. Each transport region contains one hole gas, centered at each edge of the Ge plateau. Each hole gas has a finite spatial extent, such that half the carriers overlap the defected transition region beyond each plateau edge. This also degrades the mobility of carriers residing in these defected regions. Equally important, hole mobility decreases when holes travel in a region of reduced Ge content, as is the case in all prior SiGe channel MOSFET designs.
In U.S. patent application Ser. No. 07/351,630, filed May 15, 1989, now U.S. Pat. No. 5,019,882 and assigned to the same assignee as the present invention, there is disclosed a MOSFET having a SiGe channel layer grown on a Si substrate. A silicon cap layer separates the silicon dioxide insulator layer from the channel layer. A suitably applied voltage will result in a region of high mobility charge carriers at the interface between the SiGe alloy layer and the silicon cap layer. This region will contain a two-dimensional electron or hole gas. By forming the electron or hole gas at the SiGe/Si interface rather than the Si/SiO.sub.2 interface as in previous devices, interface scattering is decreased or eliminated. The region of high mobility charge carriers is as near as possible to the gate (at the Si/SiGe interface), and thus the capacitance is maximized and device performance is enhanced. However, carrier mobility is actually at its lowest nearest the gate. Hence, the device transconductance, which is a figure of merit that is linearly proportional to both capacitance and mobility is not optimized. Furthermore, the channel region described in this earlier work is symmetric as in all known prior art. The abrupt transitions between silicon and silicon germanium regions in such a symmetric structure result in a number of carriers being transported outside of the channel region.
Thus, it is desirable to provide a MOSFET type device having a SiGe channel with optimized transconductance in order to increase the amount of current that can be passed through the device.